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Greg White - BSEE - ASIC Expert

I am an Electrical Engineer (BSEE, from University of Wisconsin, Madison) and a US Citizen with eighteen years experience with logic design, verification and synthesis of state of the art digital high speed ASICs (Application-Specific ICs) and programmable logic.

Experience

ASIC Design and Verification.

  • Logic Design and Synthesis using Hardware Design Languages VHDL and Verilog using with the latest EDA tools that the client has available.

  • Verification of digital IC designs using SystemVerilog, Verisity Specman "e" language, Vera, C and C++ programming languages, an scripting tools such as PERL, TCL, shell scripting and make files.

  • Work is performed either at the client's site in the Silicon Valley area of California at my own site.

  • I have led trainings for design engineers in various topics of IC methodology including VHDL and Verilog design languages.
    • - ASIC Design and Verification Consulting