IC design verification consulting done primarily at our Silicon Valley office facilities.
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Education
BSEE (Bachelor of Science in Electrical and Computer Engineering) from University of Wisconsin, Madison
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Experience
US Citizen with eighteen years experience with logic design, verification and synthesis of digital ASICs (Application-Specific ICs) and programmable logic.
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ASIC Design and Verification
Verification of digital IC designs using SystemVerilog with OVM, Verisity Specman "e", Vera with RVM, C and C++ programming languages, PERL, TCL, shell scripting and make files.
Logic Design and Synthesis
Trainings for design engineers for language and applications of Hardware Design Languages and methodology.
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