ASIC and FPGA Design Verification Consulting
Greg White - BSEE
20 years experience in ASIC Verification
IC design verification consulting done in the Silicon Valley office.
BSEE (Bachelor of Science in Electrical and Computer Engineering) from University of Wisconsin, Madison
US Citizen with over twenty years experience with logic design, verification and synthesis of digital ASICs (Application-Specific ICs) and programmable logic.
ASIC and FPGA Design and Verification
- Verification of digital IC designs using SystemVerilog with OVM, Verisity Specman "e", Vera with RVM, C and C++ programming languages, PERL, TCL, shell scripting and make files.
- Logic Design and Synthesis
- Trainings for design engineers for language and applications of Hardware Design Languages and methodology.
Here is a sample of products to which I contributed as part of a product team:
- IPODs and other MP3 devices
- 3D Video Graphics Processors
- Cell phones
- Satellites and Earth stations
- Packet endoders and decoders
- Avionics video processors
- RISC processors
- RAID system
- RISC CPU L2 Memory Cache
- Fiberoptic Data Link
- Class 5 Central Office Telephone Switches for ISDN
- Cellular Mobile Telephone Base Stations