Clients include

ASIC and FPGA Design Verification Consulting
Greg White - BSEE - ASIC Expert

IC design verification consulting done primarily at our Silicon Valley office facilities.

Education

BSEE (Bachelor of Science in Electrical and Computer Engineering) from University of Wisconsin, Madison

Experience

US Citizen with eighteen years experience with logic design, verification and synthesis of digital ASICs (Application-Specific ICs) and programmable logic.

ASIC Design and Verification

  • Verification of digital IC designs using SystemVerilog with OVM, Verisity Specman "e", Vera with RVM, C and C++ programming languages, PERL, TCL, shell scripting and make files.
  • Logic Design and Synthesis
  • Trainings for design engineers for language and applications of Hardware Design Languages and methodology.
  • Open Verification Methodology
    System Verilog
    System Verilog
    View Greg White's profile on LinkedIn
    IEEE Consultants' Network of Silicon Valley