- Logic, System and Circuit Design using Verilog and VHDL with Synopsys and Cadence
- Timing Analysis
- Timing Backannotation to Netlist
- Static timing analysis
- Equivalency checking
- Design-for-test
- Scan insertion
- Complete to tape out and post routing
|
Target devices:
- Digital ASICs (Application Specific ICs)
- Programmable Logic Design
- Gate Arrays
- FPGAs
- PALs
|
- Design,
- Synthesis
- Verification
- Programming
- Machine Language Coding
- Assembler Language Coding
|
EDA tools:
- Cadence NCSim, Verilog-XL PLI, VPI Leapfrog, hal, lint
- Model Technology V-System VHDL Simulation
- Mentor Design Architect, Autologic, NetEd, Modelsim
- Synopsis DC Shell, Design Analyzer, VERA, Test compiler, HDL Advisor, VSS, VCS, Timemill
- Icarus Verilog - simulation and synthesis
|
Processor Design:
- 3D Video Graphics Processors
- Avionics Video Processors
- RISC Processors
- Memory Cache
|
System and Hardware Design of Telecommunications Systems:
- Asynchronous Transfer Mode (ATM)
- Utopia Bus
- Fiberoptics
- ISDN
- Class 5 Central Office Telephone Switches
- Cellular Mobile Telephone Base Stations
|
Analog Design
- TDMA (Time Division Multiple Access)Modulators/Demodulators
- High Speed Clock/Data Synchronization
- Tone Generators
- Tone Detectors
- Phase Locked Loops
- Injection locked oscillators
- Analog and digital modems
|
MICROPROCESSORS AND INTERFACES USED IN DESIGN AND VERIFICATION of SYSTEMS
- AMD 2900 family
- Intel 80960, 80186, 8080, 8085, 8051
- Motorola 6800
- Texas Instruments TMS320C30 DSP
- Zilog Z80, Z80B
- PCI Bus
- VMEBus
- IEEE-488 Bus
- ATA-66 Bus
- ATAPI 6 and 7
- Utopia Bus
- SPI Bus
- MBUS
- Several other proprietary busses
|
