EXPERIENCE SUMMARY

• Logic, System and Circuit Design using Verilog and VHDL with Synopsys, Mentor and Cadence simulators and tools
• Verification
  • Test suites comprising Object Oriented System Verilog and Vera for constrained random and directed tests
  • Verilog test benches for directed tests utilizing scripting in PERL, C, C++, Sed, Awk and TCL
  • Full regression testing
  • Design debugging based on verification
  • Full system simulation
  • Gate level simulation including timing backannotation to netlist
  • Static timing analysis
  • Equivalency checking

• IPODs and other MP3 devices
• 3D Video Graphics Processors
• Cell phones
• Satellites and Earth stations
• Packet endoders and decoders
• Avionics video processors
• RISC processors
• RAID system
• CPU L2 Memory Cache
• Asynchronous Transfer Mode (ATM)
• Utopia Bus
• Fiberoptics
• ISDN
• Class 5 Central Office Telephone Switches
• Cellular Mobile Telephone Base Stations

• TDMA (Time Division Multiple Access)Modulators/Demodulators
• High Speed Clock/Data Synchronization
• Tone Generators
• Tone Detectors
• Phase Locked Loops
• Injection locked oscillators
• Analog and digital modems

• Object Oriented System Verilog with OVM class libraries
• Object Oriented Vera with RVM class libraries
• VHDL with C interface
• Synopsys DC Shell
• Verisity e (Specman)
• Verilog with PLI and VPI
• C
• Java
• C++
• PERL
• PHP
• sed
• awk
• FORTRAN
• BASIC
• TI-DSP
• Authored an assembler language for programming a CDC bus interface simulator
• Z80 assembler
• 8085 assembler
• 8051 assembler
• MACRO-11 assembler
• Microtek microcode
• AMD 2900 microcode
• VIGEN
• MISL
• ABEL
• CUPL
• PALASM