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Clients include
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ASIC and FPGA Methodology Training
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We lead workshops in - VHDL language and applications
- Verilog language and applications
- System Verilog Object Oriented (OO) language and verification methodology
- System Verilog Assertions (SVA) language and applications to verification
- Scripting Languages and Methodologies used for Design Verification
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With years of hands-on design experience I'm able to provide a practical as well as theoretical background to enhance the trainee's experience.
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These seminars immerse the design engineer into a thorough working knowledge of designing and doing verification with these HDL languages.
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For availability information, contact Greg White
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