|
|
Clients include
 
|
|
|
ASIC and FPGA Methodology Training
|
We lead workshops in - VHDL language and applications
- Verilog language and applications
- System Verilog Object Oriented (OO) language and verification methodology
- System Verilog Assertions (SVA) language and applications to verification
- Scripting Languages and Methodologies used for Design Verification
|
|
With years of hands-on design experience I'm able to provide a practical as well as theoretical background to enhance the trainee's experience.
|
|
These seminars immerse the design engineer into a thorough working knowledge of designing and doing verification with these HDL languages.
|
For availability information, contact Greg White
|
