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ASIC and FPGA Design Verification Consulting Greg White - BSEE - ASIC Expert

IC Logic Verification
The IC design process in the past few years has changed significantly: currently verification encompasses a large portion of the effort. "Getting it right" is mandatory, not just for ASICs which have huge respin penalties for design bugs, but for Programmable Logic. With Programmable Logic it is possible to use an early draft of the RTL design to synthesize and realize the design on an FPGA early on, fixing the bugs later. The problem with this approach is that FPGA or ASIC testing by itself does not come close to the sophistication of modern test methods which utilize constrained random and directed tests. By automating the verification process, the target Device Under Test (DUT) is bombarded with a large set of random stimuli which can find statistically unlikely combinations of events which could cause bugs and would almost never be uncovered by using only deliberate, directed tests.
Recent Verification Experience:
Functional Verification - Constrained Random and Directed tests Object-Oriented System Verilog with OVM libraries Object-Oriented VERA with RVM libraries Verisity Specman Verilog with file driven stimulus and response Verilog C/C++ interfaces (PLI, VPI) and scripting (SED, AWK, PERL) Formal Verification Terasystems Teraform formal verification tools Cadence's Incisive Formal Verifier tool
Types of Digital Designs which have been verified: 3D video graphics processors Avionics video processors Network routers Controllers/CPUs using microcode in verification process Cell phones Central office voice and packet switch Packet encoders Serial and Parallel consumer interfaces Printer interfaces RISC Processors L2 memory cache (functional and performance verification)

Open Verification Methodology

System Verilog

System Verilog

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