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ASIC Verification

VERIFICATION EXPERIENCE SUMMARY

  • Creation of test plans
  • full test suites
  • test benches
  • test vector generation
  • scripting in PERL, C, C++, Sed, Awk and TCL, Verisity Specman, VERA
  • Full regression testing
  • RTL debugging based on verification
  • Full circuit and system simulation RTL, behavioral, gate level
VHDL and Verilog, using
  • Cadence NCSim, Verilog-XL PLI, VPI Leapfrog, hal, lint;
  • Model Technology V-System VHDL Simulation
  • Mentor Design Architect, Autologic, NetEd,
  • Synopsis DC Shell, Design Analyzer, VERA, Test compiler, HDL Advisor, VSS, VCS, Timemill
Processor Design and Verification:
  • 3D Video Graphics Processors,
  • Avionics Video Processors
  • RISC Processors
  • Memory Cache